1. Technical Field
The present invention relates to optical communication and fiber optic transmission systems, and more particularly to a system and a method for testing a high-speed ADC in a DP-QPSK receiver.
2. Description of Related Art
Recently, the combination of phase shift keying technology and coherent detection has provided efficient spectrum utilization. As compared to the traditional direct intensity encoding and direct detection, DP-QPSK (Dual-Polarization Quadrature Phase Shift Keying) improves every transmission wavelength in information-carrying capability significantly.
DP-QPSK encodes and demodulates signals on the principle described below. A signal is split to two when passing a polarization beam splitter, and then the two signals get coupled with two light beams of a local oscillator generated by a polarization-maintaining intensity-splitting prism in two 90° phase shifters. Each 90° phase shifter has two arms and a differential output. In the path having the local oscillator, the lower arm is one-quarter cycle longer than the upper arm. The 90° phase shifters are followed by 8 photoelectric detectors (PD) or 4 sets of balanced photoelectric detectors. What is seen in the upper arm balanced photoelectric detector is in-phase beat product, and what is seen in the lower arm balanced photoelectric detector is quadrature beat product. The differential signals generated by the balanced photoelectric detectors are converted into voltage signals by a subsequent transimpedance amplifier. The transimpedance amplifier has its differential output converted from analog to digital one and then enters the successive digital signal processing module (DSP) for data recovery. In the DSP, the most critical part is its high-speed analog-to-digital converter chip, which converts analog signals into digital signals for further algorithmic processing.
The existing methods for testing a high-speed ADC in a DP-QPSK system have innate shortcomings. For example, it is costly to build a complete high-speed DP-QPSK system with hardware, and since ADCs are usually integrated in commercial DSPs, it is difficult to test them separately. Besides, complicated FPGA algorithms have to be developed for testing.